Dynamic random access memory (DRAM) is utilized in numerous electronic systems. A continuing goal is to increase the level of integration, with a corresponding goal to decrease the size of memory devices. As the design rule of memory devices decreases, channel doping within transistors associated with the memory devices is increased to alleviate short channel effects. However, the increased channel doping can cause increased leakage at junctions, which can render it increasingly difficult to obtain sufficient data retention time within the memory devices.
Another continuing goal of DRAM fabrication is to decrease the refresh rate associated with DRAM. Presently, DRAM is typically refreshed several hundreds of times per second, which can be a significant drain on batteries.
In some ways, the two goals discussed above are found to be incompatible with one another. Specifically, increased integration can lead to increased leakage, requiring faster refresh rates. It is desired to develop DRAM structures which can be formed to high levels of integration, and yet which can have low refresh rates; and to develop methods of forming such structures.
Although the invention was motivated, at least in part, by a desire to improve memory constructions (such as, for example, DRAM constructions), it is to be understood that the invention described herein can have additional applications besides utilization for memory constructions.